Introduction To Vhdl - Udemy

What you'll learn
Implement their own VHDL designs on a FPGA / CPLD
Interpret a digital design written in VHDL
Simulate their own VHDL designs
Understanding of the capabilities of VHDL
Requirements
You should have a basic knowledge of digital logic gates
You should be comfortable with using a computer
Download & install Vivado (the link is provided in the course)
Download & install ModelSim (the link is provided in the course)
Description
Introduction to VHDL is a course that someone with no experience or knowledge of VHDL can use to learn and understand the VHDL language. In this course students will learn about all of the different data types associated with the VHDL language. This course focuses on teaching students how the syntax of VHDL is interpreted and how it can be used to design circuits. There are over 8 different examples digital designs implemented in VHDL.Course StructureThis course starts out by explaining the background and history of VHDL and it's uses. Then students will learn about all the different objects and data types associated with VHDL. There are various examples showing the data types in use and how different objects behave in different applications. After learning about the data types and objects, students will then learn about the keywords and syntax of the VHDL language. Then students will learn about all of the different design architectures used in VHDL. Students will also learn how to design a test bench to simulate and verify functionality of their designs. This knowledge will then be used to complete the final project, tying in all facets of the VHDL language.VHDL DesignsThis course has many design...

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